1. Field of the Invention
The present invention relates to a decoder circuit, more particularly, to a decoder circuit of a programmable read only memory (which includes, for example, an erasable programmable read only memory: EPROM or a one time programmable read only memory: OTPROM) having a plurality of floating gate avalanche injection MOS (FAMOS) transistors as memory cells.
2. Description of the Related Art
Generally, an EPROM comprises a cell matrix portion (memory cell array) formed by a plurality of FAMOS transistors as memory elements (memory cells), bit lines and word lines for selecting a specific memory cell, and decoder circuit for driving them. In the decoder circuit of the EPROM, a power supply voltage is brought to a low voltage (for example, 5 volts) at the time of reading out (reading-out time), a memory cell corresponding to an address signal (of which the voltage value is, for example, at 0 volts or 5 volts) is selected and data is output therefrom. On the other hand, at the time of writing (writing time), the power supply voltage is brought to a high voltage (for example, 12.5 volts), and the writing operation is carried out thereby. Namely, the memory cell of a FAMOS transistor is written by using the high voltage of 12.5 volts.
Recently, a decoder circuit of an EPROM comprising a NAND gate circuit including a load transistor and a plurality of decoder transistors and a CMOS inverter circuit receiving an output of the NAND gate circuit is proposed (which is, for example, disclosed in Japanese Unexamined Patent Publication No. 61-45496). In this decoder circuit, a booster circuit for a writing operation is not provided between the NAND gate circuit and the CMOS inverter circuit, as the NAND gate circuit comprises the load transistor used as a constant current source and is supplied with a power supply voltage changeable between a high voltage Vpp (12.5 volts) and a low voltage Vcc (5 volts). Namely, in the case of writing of the EPROM, an output of the NAND gate circuit of this decoder circuit is already at a high voltage level Vpp by receiving the high voltage Vpp, and thus the booster circuit for boosting an output (which is at a low voltage level Vcc) of a conventional NAND gate circuit to a high voltage level Vpp is not required. Therefore, this decoder circuit (for example, shown in JPP'496) is preferable for a large scale integration of an EPROM, as the booster circuit is not required.
Incidentally, in the NAND gate circuit, a plurality of parasitic capacitors are formed at connection points among the decoder transistors. Note, the ability to supply the current of the load transistor is not large, and thus in the case of a plurality of parasitic capacitors being charged, a potential drop at the output of the NAND gate circuit is caused and an erroneous operation of the EPROM may be caused (which is described in later in detail).